As semiconductor devices are scaled-down, a variety of operational and structural problems may result. For example, in field-effect transistors (FETs) having a planar channel region, problems may occur when the length of the channel region is reduced to 100 nm and below. More particularly, planar channel FETs may include gate electrodes that are formed on a planar channel region. Since an electric field at upper and lower portions of the channel may be asymmetrical, the capacity of the gate to control the channel may become deteriorated as channel length is decreased. In order to improve the control capacity of the gate with respect to the channel, double-gate field effect transistors and/or triple-gate field effect transistors have been developed. In double- and triple-gate field effect transistors, the gate electrode may be formed to be in contact with multiple sides of the channel. As such, a more symmetrical electric field may be applied to the channel, which may thereby improve the control capacity of the gate with respect to the channel. As a result, it may be possible to better suppress short channel effects.
Double-gate fin field-effect transistors (FinFETs) are disclosed in U.S. Pat. No. 6,396,108 entitled “SELF-ALIGNED DOUBLE GATE SILICON-ON-INSULATOR (SOI) DEVICE”. FinFET devices may include a fin-shaped active region vertically protruding from a semiconductor substrate. Since the height of the fin may be greater than the thickness thereof, a conductive layer may be formed on the fin so as to form a gate electrode on an upper portion and sidewalls of the fin. However, in some instances, the shape of the fin may be altered due to over-etching of the fin when the gate electrode is formed.
Furthermore. FinFET devices may be capable of driving relatively high current through the channel at two and/or three sides of the fin. Therefore, in order to improve the control capacity of the gate with respect to the channel, the width/thickness of the fin may reduced, and wider source/drain regions may be formed in order to output the high current.